1. Field of the invention
The present invention relates to a memory cell array which can improve a program efficiency.
2. Brief Description of the Prior Art
In general, a non-volatile memory device having functions of electrical program and erasure is composed of a memory cell array and a peripheral circuit. The memory cell array consists of a plurality of memory cells, each of the memory cells is selected by word line and bit line signals. And an information is stored to the memory cell. The program operation for storing an information to each memory cell is performed by injection of a hot carrier to a floating gate, and erasing operation is performed by discharge of the injected hot carrier due to tunnelling. Therefore, the degree of generation of hot carriers is an important factor for decision of program efficiency of the memory cell.
In addition, the memory cell has a gate electrode of a stack or split structure. Now, a conventional memory cell array composed of memory cells having a gate electrode of the stack structure is described below with reference to FIGS. 1 and 2.
FIG. 1 is a lay-out to illustrate the conventional memory cell array. Field oxide films 9 are formed in isolation regions, respectively, of a silicon substrate 1, and control gates 7 are formed on the substrate 1 in right angle with the field oxide films 9. A plurality of floating gates 5 including a portion of the field oxide film 9 are formed below each control gate 7. Drain regions 3 are formed in active regions A1 corresponding to the inside of each control gate 7, and source regions 2 are formed in active regions A2 corresponding to the outside of each control gate 7. In addition, contact portions 8 for contact with a bit line which is extended to cross the control gates 7 are formed in the drain regions 3, respectively.
FIG. 2 is a cross sectional view taken along a line 2A--2A and shows a non-volatile memory cell having a stack structure as described above. In the non-volatile memory cell, a gate electrode 10 composed by sequentially forming a tunnel oxide film 4, the floating gate 5, a dielectric film 6 and the control gate 7 is formed on a channel region of the silicon substrate 1. The source and drain regions 2 and 3 are formed at both sides of the gate electrode 10.
The program operation of the memory cell array constructed as described above is described below.
If program bias voltages are applied to the control gate 7, drain region 3 and source region 2 of memory cell to be programmed, respectively, a horizontal electric field is formed in the silicon substrate 1. At this time, a channel pinch-off region is formed at the edge of the drain region 3, therefore, the strength of an electric field is maximized at the periphery of the drain region 3. In this condition, in the process where electrons move from the source region 2 along a channel formed at the space of the silicon substrate 1, the electrons pass through a high electric field around the drain region 3 to be accelerated and obtain substantial energy. Such electrons are called hot carrier. Such accelerated electrons (hot carrier) strike against a crystal of silicon in the drain region 3, therefore, the electrons shifted a direction of movement. As the result, a part of electrons which change their path to the floating gate 5 run over an energy barrier of silicon oxide film by the effect of a vertical electrical field which is induced in a direction from the control gate 7 to floating gate due to a capacitor coupling, and then the electrons are injected into the floating gate 5. The memory cell is programmed by a drain side injection of hot carrier as described above.
Electrons which struck against the silicon atoms have probability of being rebound in any direction from the impact place due to the impact ionization effect. However, since only the electrons which are rebounded to the floating gate 5, that is, in the vertical direction are injected into the floating gate 5, the efficiency of the program is lowered.